1. Field of the Invention
The present invention relates to a dc-offset canceler circuit and a differential amplifier circuit and more particularly, to a dc-offset canceler circuit which is preferably used for an amplifier circuit amplifying a signal in a low-frequency region such as 1 kHz to 10 kHz (e.g., the baseband frequency region) in a portable telecommunication system such as a pager system, and a differential amplifier circuit equipped with the dc-offset canceler circuit.
2. Description of the Prior Art
In recent years, a direct conversion receiver has been popularly used as a portable radio receiver such as a pager instead of a conventional superheterodyne receiver.
A limiting amplifier circuit designed for a direct conversion receiver of a pager amplifies a signal in the baseband frequency region (typically, 1 kHz to 10 kHz). This limiting amplifier circuit has a configuration that a plurality of differential amplifier subcircuits are cascade-connected at a plurality of stages, in which the differential amplifier subcircuits located at two adjoining ones of the stages are directly coupled without coupling capacitors. This is due to the following reason.
The coupling capacitor needs to have a large capacitance for the signal in the baseband frequency region and as a result, this capacitor occupies a large area on an Integrated Circuit (IC) chip. Accordingly, the coupling configuration with the coupling capacitor having such the large capacitance is not suitable to ICs. On the other hand, the directly coupling configuration requires no coupling capacitor and therefore, no problem relating to the chip area will occur.
With the limiting amplifier circuit having the direct-coupling configuration, the "dc offset" generated in the differential amplifier subcircuits at the respective stages tends to cause some known problems. To solve the problems, various techniques have been studied and developed for a long time, an example of which is shown in FIG. 1.
FIG. 1 shows a conventional dc blocking amplifier circuit having a dc-offset canceling function, which is disclosed in the Japanese Non-Examined Patent Publication No. 2-305205 published in 1990.
As shown in FIG. 1, the conventional dc blocking amplifier circuit S300 includes a first differential amplifier subcircuit S100 and a second differential amplifier subcircuit S200, which are coupled together by an ac-coupling capacitor 113.
The first differential amplifier subcircuit S100 is comprised of an emitter-coupled pair of npn-type bipolar transistors 101 and 102. The coupled emitters of the transistors 101 and 102 are connected to one end of a constant current sink 111 sinking a constant current I.sub.101. The other end of the constant current sink 111 is connected to the ground.
A resistor 109 is connected to the bases of the transistors 101 and 102. The base of the transistor 101 is further connected to a first input terminal 114. The base of the transistor 102 is further connected to one end of the coupling capacitor 113.
The second differential amplifier subcircuit S200 is comprised of an emitter-coupled pair of npn-type bipolar transistors 103 and 104. The coupled emitters of the transistors 103 and 104 are connected to one end of a constant current sink 112 sinking a constant current I.sub.102. The other end of the constant current sink 112 is connected to the ground.
A resistor 110 is connected to the bases of the transistors 103 and 104. The base of the transistor 103 is further connected to the other end of the coupling capacitor 113. The base of the transistor 104 is further connected to a second input terminal 115.
First and second input voltages are differentially applied across the first and second input terminals 114 and 115, respectively.
Collectors of the transistors 101 and 103 are coupled together to be connected to an end of a load resistor 107. The other end of the load resistor 107 is applied with a power supply voltage V.sub.CC. The coupled collectors of the transistors 101 and 103 are further connected to a first output terminal 116.
Collectors of the transistors 102 and 104 are coupled together to be connected to one end of another load resistor 108. The other end of the load resistor 108 is applied with the power supply voltage V.sub.CC. The coupled collectors of the transistors 102 and 104 are further connected to a second output terminal 117.
First and second output voltages are differentially derived from the first and second output terminals 116 and 117, respectively.
The transistors 101, 102, 103, and 104 have a same emitter area.
Next, the operation of the conventional dc blocking amplifier circuit S300 in FIG. 1 is explained below.
First, base voltages of the transistors 101, 102, 103, and 104 with respect to a specific reference point (e.g. the ground) are defined as V.sub.B101, V.sub.B102, V.sub.B103, and V.sub.B104, respectively. Collector currents of the transistors 101, 102, 103, and 104 are defined as I.sub.C101, I.sub.C102, I.sub.C103, and I.sub.C104, respectively. First and second output currents flowing through the load resistor 107 and 108 are defined as I.sub.C113 and I.sub.C124, respectively.
Then, the following equations (1) and (2) are established. EQU I.sub.C113 =I.sub.C101 +I.sub.C103 ( 1) EQU I.sub.C124 =I.sub.C102 +I.sub.C104 ( 2)
The collector currents I.sub.C101, I.sub.C102, I.sub.C103, and I.sub.C104 of the transistors 101, 102, 103, and 104 are expressed as the following equations (3), (4), (5), and (6), respectively. ##EQU1##
In the equations (3), (4), (5), and (6), .alpha. is the dc common-base current gain factor of each transistor, k is the Boltzmann's constant, T is absolute temperature in degrees Kelvin, and q is the charge of an electron. Typically, the gain factor a is approximately equal to 1.
When the constant current I.sub.102 of the constant current sink 112 is equal to the constant current I.sub.101 of the constant current sink 111 (i.e., I.sub.101 =I.sub.102), and the difference between the base voltages V.sub.B104 and V.sub.B103 of the transistors 104 and 103 are equal to the difference between the base voltages V.sub.B101 and V.sub.B102 of the transistors 101 and 102 (i.e., V.sub.B101 -V.sub.B102 =V.sub.B104 -V.sub.B103), the first and second output currents I.sub.C113 and IC.sub.124 become equal to each other. If the load resistors 107 and 108 have a same resistance, the first and second output voltages will have a same dc level at the first and second output terminals 116 and 117.
If the dc voltage level of the first input voltage at the first input terminal 114 is higher than that of the second input voltage at the second input terminal 115 due to a dc offset, the base voltages V.sub.B101, V.sub.B102, V.sub.B104, and V.sub.B103 satisfy the relationships of
V.sub.B101 &gt;V.sub.B102 and PA1 V.sub.B104 &lt;V.sub.B103.
In this case, the collector current I.sub.C101 increases by an increment and the collector current I.sub.C102 decreases by the same increment in the first differential amplifier subcircuit S100. At the same time, the collector current I.sub.C103 increases by an increment and the collector current I.sub.C104 decreases by the same increment in the second differential amplifier subcircuit S200. Therefore, the first output current I.sub.C113 is increased and the second output current I.sub.C124 is decreased.
Thus, the dc voltage level at the first output terminal 116 is lowered and that at the second output terminal 117 is raised, thereby canceling the dc-voltage level difference (i.e., the dc offset) at the first and second input terminals 114 and 115. This means that no dc offset is generated between the first and second output terminals 116 and 117 even if the dc offset exists between the first and second input terminals 114 and 115.
The dc voltage levels at the first and second output terminals 116 and 117 are determined by a specific dc bias voltage applied to the conventional dc blocking amplifier circuit S300.
The same explanation as above is applied to the case where the dc voltage level at the first input terminal 114 is lower than that at the second input terminal 115.
However, the conventional dc blocking amplifier S300 in FIG. 1 has the following problem.
If any difference is generated between the constant currents I.sub.101 and I.sub.102 of the constant current sinks 111 and 112 (i.e., I.sub.101 .noteq.I.sub.102) due to the dc-voltage level difference greater than a specific value at the first and second input terminals 114 and 115, there arises a problem that a dc offset tends to occur between the first and second output terminals 116 and 117. It was found by the inventor that this problem is caused by the fact that the transistors forming one of the constant current sinks 111 and 112 operate in the saturation region while those forming another one of the constant current sinks 111 and 112 operate in the active region, resulting in some difference between the constant currents I.sub.102 and I.sub.102.
The dc bias offset thus generated at the first and second output terminals 116 and 117 is amplified by a differential amplifier located at a next stage. Therefore, there arises a disadvantage that the gain of the amplifier at the next stage needs to be set as sufficiently low.
Because of this problem, the conventional dc blocking amplifier S300 in FIG. 1 is not suitable to a dc-offset canceler for the limiting amplifier of the above sort.
Additionally, the difference between the constant currents I.sub.101 and I.sub.102 of the constant current sinks 111 and 112 may occur due to any other cause such as the unbalance in device layout of the current sinks 111 and 112.